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78p7200l e3/ds3/sts-1 transceiver march 2001 description the 78p7200l is a line interface transceiver ic for e3, ds3, sts-1, north america t3 and atm applications. it includes clock recovery and transmitter pulse shaping functions for applications using 75-ohm coaxial cable at distances up to 1100 feet. these applications include dslams, t3/e3 digital multiplexers, sonet add/drop multiplexers, pdh equipment, ds3 to fiber optic and microwave modems and atm wan access for routers and switches. the receiver recovers clock and positive data and negative data from an ami signal. it can compensate for over 12db of cable and 6db of flat loss. the transmitter generates a signal that meets the standard pulse shape requirements. the 78p7200l is pin and functionally compatible to the 78p7200. it adds loop-back and clock polarity selection. the 78p7200l is manufactured in an advanced bicmos process and operates at both 5v and 3.3 v power supply voltages. it consumes less than 95 ma of supply current. features ? single chip transmit and receive interface for e3, ds3 and sts-1 applications. ? interface to 75 ohm coaxial cable over 1100 feet at speeds up to 51.84 mbps. ? compliant with ansi t1.102-1993, telcordia gr-499-core and gr-253-core, itu-t g.703 and g.823 for jitter tolerance. ? compliant with atm forum af-phy-0034 (e3 public uni) and af-phy-0054 (ds3 public uni). ? easily interfaced to atm framer ics such as pmc 7345 , 7346 qjet and 7321. ? unique clock recovery requires no reference clock or crystal oscillator. ? receive ds3-high signal ? includes diagnostic loop-back for ami and digital signals. ? pin compatible to 78p7200 and 78p2241 (28- lead plcc). ? 28-lead plcc and 48-lead tqfp packages ? 3.3 or 5 v operation, icc<95ma ? input circuit works either transformer or capacitor coupled block diagram pulse shaper cloc k reco very adaptiv e equalizer data slicer los linn linp loutn loutp tpos lpbk lf signal detector tneg ami to binary binary to ami tclk rclk rpos rneg biasing rfo lpbk lbo txen tdk semiconductor corp. ?
78p7200l e3/ds3/sts-1 transceiver 2 functional description the 78p7200l is a single chip line interface ic designed to work with a 51.84 mbit/s sts-1, 44.736 mbit/s ds3 or 34.368 mbit/s e3 signal. the receiver recovers clock, positive data and negative data from an alternate mark inversion (ami) signal. the ami line input signal should be b3zs or hdb3 coded. the transmitter accepts clock, positive, and negative data and converts them into an ami signal to drive a 75 ? coaxial cable. the shape of the transmitted signal t hough any cable length of 0 to 450 feet complies with the published templates of ansi t1.102-1993, telcordia tr-nwt-000499 and gr-253-core, itu-t g.703. the 78p7200l is designed to work with b3zs or hdb3 coded signals. the b3zs or hdb3 encoding and decoding functions can be included in the framer ics. the 78p7200l is designed to easily connect to popular atm framer ics such as pmc 7345 (suni- pdh), pmc 7346 (qjet) and 7321. operation speed internal bias generators that are adjusted by the value of the rfo set the 78p7200l pll center frequency and transmitter amplitude for the different standards. the e# pin controls the equalizer response and the transmitter pulse shape and amplitude. the following table shows the proper settings. standard rfo value, k ? ? ? ? e# e# e# e# pin setting e3 6.81 low ds3 5.23 high sts-1 4.53 float receiver the receiver input can be either transformer-coupled or capacitor coupled to the ami signal. in applications where the highest performance and isolation is required, a 1:1 transformer is used on the receiver path. in the applications, where isolation is provided elsewhere in the circuit, an ac coupling can be used. the inputs to the ic are internally referenced to vcc. since the input impedance of the 78p7200l is high, the ami line must be terminated to 75 ? . the input signal of the 78p7200l must be limited to a maximum of three consecutive zeros using a coding scheme such as b3zs or hdb3. the ami signal first enters an equalizer and agc gain stage. the equalizer is designed to overcome intersymbol interference caused by long cables. because the equalizer is adaptive, the circuit will work with all square shaped signals such as ds3 high or 34 mbit/s e3. the variable gain differential amplifier maintains a constant voltage level output regardless of the input voltage level. the gain of the amplifier is adjusted by detecting the peak of the signal and comparing it to a fixed reference. outputs of the data comparators are connected to the clock recovery circuits. the clock recovery system employs a phase locked loop with an auxiliary frequency-sensitive acquisition loop. this system permits the loop to independently lock to the frequency and phase of the incoming data stream without the need for an external, high precision tuned circuits or reference clock signal. the jitter tolerance of the 78p7200l meets the requirements of telcordia gr-499-core for category i equipment for ds3 rates and exceeds the requirements of itu-t g.823 for e3 rates.
78p7200l e3/ds3/sts-1 transceiver 3 functional description (continued) loss of signal should the input signal fall below a minimum value, the loss of signal indication, los goes low. transmitter the transmitter accepts logic level clock (tclk), positive data (tpos) and negative data (tneg) signals and generates current pulses on the lout+ and lout- pins. when properly connected to a center-tapped 1:2 transformer, an ami pulse is generated which can drive a 75 ? coaxial cable. when the recommended transformer is used and the e# pin is set high, the transmitted pulse shape at the end of the 75 ? terminated cable of 0 to 450 feet will fit the ds3 template in ansi t1.102-1993 and telcordia gr-499-core standard documents. for sts-1 applications, the transmitted pulse for a short cable meets the requirements of telcordiagr- 253-core. the e# pin should be allowed to float. for e3 applications, the transmitted pulse for a short cable meets the requirements of itu-t g.703. the e# pin is to be pulled low. rclk/tclk polarity reversal: to simplify the interface with framer circuitry, rclk and tclk can be inverted with the ickp pin. pin 10 ickp rclk tclk low normal normal float invert invert high normal invert loop-back modes: the following loop-back modes allow for the diagnostic test of the pc board. this function is controlled by the lpbk pin. pin 40/tqfp pin 28/plcc lpbk lpbk lpbk lpbk loop-back low local loop-back (llb) float remote loop-back (rlb) high normal operation local loop-back : when lpbk is low, the 78p7200l enters local loopback. in this mode, the lout+/- transmit signals are internally routed to the receiver input circuit. the incoming line receiver ami signal on lin+/- is ignored. with the transmitter still tied to the cable, this test mode can indicate a short circuit on the transmitter external components or other problem in the transmit path. remote loop-back: when lpbk pin is allowed to float, the 78p7200l enters remote loopback mode. the rpos/rneg and rclk pins are internally tied to the tpos/tneg and tclk so the same ami signal that is received by the framer is transmitted back to the far end where a bit continuity test can be performed. line build-out: the line build-out function controls the amplitude in ds3 and sts-1 mode. the selection of lbo depends on the amount of cable the transmitter is connected to. when used with less than 225 ft of cable the lbo pin should be pulled high. with 225ft or more cable the lbo pin should be low.
78p7200l e3/ds3/sts-1 transceiver 4 pin description: the 28-pin plcc is compatible with 78p7200 and 78p2241 name pin tqfp pin plcc type description lin+ lin- 42 44 1 3 i line input: differential ami inputs to the chip. should be transformer coupled and terminated at 75-ohm resistor. rclk 33 23 o receive clock: recovered receive clock. rpos/ rnrz 35 25 o receive positive data / nrz data: this pin indicates reception of a positive ami pulse on the coax cable. rneg 34 24 o receive negative data: this pin indicates reception of a negative ami pulse on the coax. los 39 27 o loss of signal: logic low indicates that receiver signal (lin) is below the threshold level rpos and rneg are forced low when los =0. lout+ lout- 9 11 9 11 o line out: differential ami output. requires a 2:1 center tapped transformer and 301 ? resistor. tclk 18 16 i transmitter clock input: this signal is used to latch the tpos/tnrz and tneg signals into the 78p7200l. tpos/ tnrz 16 14 i transmit positive data / transmit nrz: a logic one on this pin generates a positive ami pulse on the coax. this pin should not be high at the same time that tneg is high. tneg 17 15 i transmit negative data: a logic one on this pin generates a negative ami pulse on the coax. this pin should not be high at the same time that tpos/tnrz is high. lbo 13 12 i line build-out, transmitter: logic low used with 225ft or more of cable is used on transmit path. logic high used with less than 225ft of cable. e# 15 13 i3 ds3, e3 and sts-1 select: set low for e# applications. set high for ds3, allow to float for sts-1 operation. formerly opt! on the 78p7200. txen 22 18 i transmitter enable: when high, enables transmitter. when low, tri-states transmitter drivers, lout. this pin was called opt@ on 78p7200. ickp 10 10 i3 invert clock polarity: when low, the polarities of rclk and tclk are the same as those on the 78p7200. when set high, the polarity of tclk is inverted. when allowed to float, the polarities of both rclk and tclk are inverted. lpbk 40 28 i3 loop-back select: when high, neither loop-back is activated. when allowed to float rpos, rneg and rclk are looped back onto tpos, tneg and tclk. when low, lout is looped back onto lin. vcc 5,6,20, 21,37,38 7,17,26 p power supply. n/c 27, 28 20, 21 no connect
78p7200l e3/ds3/sts-1 transceiver 5 pin description: the 28-pin plcc is compatible with 78p7200 and 78p2241 (continued) name pin tqfp pin plcc type description gnd 1, 3, 4, 7, 8, 12, 14, 19, 23, 24, 25, 29, 30, 31, 32, 36, 41, 43, 45, 46, 47, 48 2, 4, 6, 8, 22 p ground. connecting all ground pins to a common ground plane is recommended. rfo 2 5 - a resistor to gnd sets the operational speed of the chip. rfo= 5.23k for ds3, rfo=6.81k for e3 and rfo=4.53k for sts-1. lf1 26 19 - receiver pll filter capacitor. note 1: pin type: i-input; i3-three level logic input; o-output; p-power supply. advanced data sheet pin assignment and functions are subject to change.
78p7200l e3/ds3/sts-1 transceiver 6 electrical specifications absolute maximum ratings operation beyond these maximums rating may permanently damage the device. parameter rating positive supply, v cc 6v storage temperature -65 to 150 ambient operating temperature -40 to +85 c output pin voltage (lout+, lout-) input pin voltage (lin+, lin-) v cc -2 to v cc +2 v input pin voltage, all other pins v cc +0.3 to gnd -0.3 v dc characteristics: ta = -40 to +85 c; positive supply voltage = 5v 0.5v or 3.3v 0.3v parameter pin type condition min typ max unit supply current i cc transmit and receive all ones, vcc=5v or 3.3v 70 110 ma supply current i cc transmitter disabled, txen=0 35 ma v il i 0.8 v v ih i 2.0 v i il , i ih i -10 +10 ua v il3 i3 0.5 v z im3 i3 input floating 8 10 20 k ? v ih3 i3 v cc -0.5 v i il3 , i ih3 i3 -100 +100 ua v ol o i ol =-0.1ma 0.5 v v oh o i ol =+0.1ma v cc -0.5 v
78p7200l e3/ds3/sts-1 transceiver 7 e3 ? receiver (rfo = 6.81k ? ? ? ? , e# e# e# e# is set low), receiver is transformer-coupled. parameter condition min typ max unit peak differential input amplitude, lin+, lin- see note 2 104 1200 mv pk bit error ratio in the presence of an interfering signal at receive input interfering signal power 20db below e3 signal power. both are prbs23 (2 23 -1) patterns. 10 -9 rclk rise/fall time trct 2 4 ns rclk period, trcf 29.10 ns rclk clock duty cycle 45 55 % rclk pulse width trc 14.55 ns rpos/rneg data setup time trdps cl=15 pf 7 ns rpos/rneg data hold time trdph cl=15 pf 7 note 2: 104 mv pk equals 950 mvpk at the source with 1100 feet of cable (13.2db loss).
78p7200l e3/ds3/sts-1 transceiver 8 ds3/sts-1 receiver (rfo = 5.23k ? ? ? ? for ds3 and 4.53k ? ? ? ? for sts-1, e# e# e# e# pin is set high or allowed to float), input is transformer coupled parameter condition min typ max unit peak differential input amplitude, lin+ and lin- (see note 3) signal at dsx is 360-850mvp (see note 4) 90 850 mvp peak differential input amplitude, lin+ and lin- ds3 high (see note 5) 90 1200 mvp bit error ratio in the presence of an interfering signal (is) at lin+,lin- is is a sinusoidal tone, 22.368 mhz for ds3 or 25.92mhz for sts-1. data is a prbs15 (2 15 -1) pattern. is power is 10db below data signal power. 10 -9 rclk rise/fall time trct cl=25pf 5 ns rclk period trcf ds3 sts-1 22.35 19.29 ns rclk pulse width trc ds3 sts-1 12.24 9.65 ns rpos/rneg data setup time trdps cl=15 pf 7 ns rpos/rneg data hold time trpdh cl=15 pf 7 ns note 3: signal source should meet ds3 template of ansi-t102.1993 figure 4 and sts-1 template of ansi- t102.1993 figure 5, loss characteristics of the we728a or rg 59b cable should be better than figure c2 of ansi-t102.1993. note 4: receiver can handle up to 450 feet of cable loss (5.5db) from the dsx cross-connect. note 5: case where test signal is fed directly into receiver with fast rise times violates ds3 template and normal maximum. interfering signal performance is not guaranteed in the presence of ds3 high at the input..
78p7200l e3/ds3/sts-1 transceiver 9 timing diagram: receive waveforms (e3/ds3/sts- 1) receive line input (ref) lin+/lin- rclk ickp=low or high rclk ickp=float rpos rneg trdps trdns trcf trct trc trdn trdnh trdph trct
78p7200l e3/ds3/sts-1 transceiver 10 receiver jitter tolerance e3 and ds3 jitter tolerance specifications are in itu-t g.823 and g.824. the test condition can be found in itu-t o.171. the e3 specification is the tighter of the two for frequencies greater than 20 khz. receive jitter tolerance is not tested during production test. parameter condition min nom max unit receiver jitter tolerance 12 hz to 2.78 hz 10hz to 600hz 20 khz to 800 khz 18 5 0.15 ui 0.01 0.1 1 10 100 1.e-05 1.e-03 1.e-01 1.e+01 1.e+03 1.e+05 1.e+07 e3 ds3
78p7200l e3/ds3/sts-1 transceiver 11 receiver jitter transfer function the receiver clock recovery loop filter characteristics are such that the receiver has the following transfer function. the corner frequency of the pll is approximately 50 khz. receiver jitter transfer function is not tested during production test. parameter condition min nom max unit receiver jitter transfer function below 59.6 khz 0.1 db jitter transfer function roll-off 20 db per decade -10 -9 -8 -7 -6 -5 -4 -3 -2 -1 0 1.e+01 1.e+02 1.e+03 1.e+04 1.e+05 1.e+06
78p7200l e3/ds3/sts-1 transceiver 12 e3 ? transmitter (rfo = 6.81k ? ? ? ? , e# e# e# e# = low) parameter condition (see timing diagram) min typ max unit transmitter amplitude lout+ and lout- 900 1000 1100 mvp transmitter amplitude mismatch ratio of amplitudes of positive and negative pulses measured at pulse centers 0.95 1.05 transmitter width mismatch ttpl/tthl ratio of widths of positive and negative pulses measured at pulse half amplitude 0.95 1.05 transmitter pulse width ttpl, ttpn lout+ and lout- 14.55 ns transmitter clock duty cycle, ttc/ttcf 40 60 % transmitter clock period ttcf 29.10 ns transmitter clock pulse width , ttc 14.55 ns transmitter clock transition time, rising and falling cptt/cntt 0.8 3 5 ns data setup time ttdrs 2.5 ns data hold time ttdhs 2.5 ns
78p7200l e3/ds3/sts-1 transceiver 13 ds3/sts-1 transmitter ( e# e# e# e# = high) parameter condition min typ max unit transmitter amplitude lout+ and lout- 650 800 850 mvp transmitter amplitude mismatch ratio of amplitudes of positive and negative pulses measured at pulse peaks. 0.9 1.1 transmitter power at 22.368 mhz ds3 only - all ones, 3khz bandwidth -1.8 +5.7 dbm transmitter power at 44.736 mhz ds3 only - all ones, 3khz bandwidth -21.8 -14.3 dbm transmitter clock duty cycle, ttc/ttcf 40 60 % transmitter clock period ttcf ds3 22.35 ns transmitter clock period ttcf sts-1 19.29 ns data setup time ttpds 2.5 ns data hold time ttpdh 2.5 ns transmitter clock transition time, rising and falling ttcpt,ttcnt 0.8 2 4 ns
78p7200l e3/ds3/sts-1 transceiver 14 timinging diagram: transmitter waveforms (e3/ds3/sts-1) tclk ickp=high or float tclk ickp=low tpos ttcf ttcpt vp vn 0.5 vp 0.5 vn ttc ttpds ttnds ttpl ttnl ttndh ttpdh ttcnt
78p7200l e3/ds3/sts-1 transceiver 15 e3 transmit template 17 ns 8.65 ns 14.55 ns 12.1 ns 24.5 ns 29.1 ns 0.1 0.1 0.1 0.1 0.1 0.1 0.2 0.2 0 0.5 1.0 0.2
78p7200l e3/ds3/sts-1 transceiver 16 ds3 transmit pulse template time axis range (ui) normalized amplitude equation upper curve -0.85 < t < -0.68 0.03 -0.68 < t < 0.36 0.03 + 0.5{1+sin[(pi/2)(1+t/0.34)]} 0.36 < t < 1.4 0.08+0.407 e -1.84(t-0.36) lower curve -0.85 < t < -0.36 -0.03 -.0.36 < t < 0.36 -0.03 + 0.5{1+sin[(pi/2)(1 + t/0.18)]} 0.36 < t < 1.4 -0.03 -0.2 0 0.2 0.4 0.6 0.8 1 1.2 -1 -0.5 0 0.5 1 1.5 time, unit intervals normalized amplitude
78p7200l e3/ds3/sts-1 transceiver 17 sts-1 transmit pulse template sts-1 (transmit template specs) time axis range (t) normalized amplitude equation (a) upper curve -0.85 < t < -0.68 0.03 -0.68 < t < 0.26 0.03 + 0.5{1+sin[(pi/2)(1+t/0.34)]} 0.26 < t < 1.4 0.1+0.61 e -2.4(t-0.26) lower curve -0.85 < t < -0.38 -0.03 -0.38 < t < 0.36 -0.03 + 0.5{1+sin[(pi/2)(1 + t/0.18)]} 0.36 < t < 1.4 -0.03 -0.2 0 0.2 0.4 0.6 0.8 1 1.2 -1 -0.5 0 0.5 1 1.5 time, unit intervals normalized amplitude
78p7200l e3/ds3/sts-1 transceiver 18 transmitter output jitter the transmit jitter specification ensures compliance with itu-t g.823 and g.824, and ansi t1.102-1993 for all supported rates. transmit output jitter is not tested during production test. transmitter output jitter detector measured jitter amplitude 10hz 800khz 20db/decade parameter condition min nom max unit transmitter output jitter 10 hz to 800 khz 0.1 ui
78p7200l e3/ds3/sts-1 transceiver 19 e3/ds3/sts-1 example circuit note 6: pin names in ( ) denote pin names from 78p7200. pin numbers refer to 28 plcc package. default settings used to simulate 78p7200. note 7: resistors on tclk, tneg, tpos are optional but recommended. clock pulse shapes at the inputs to the 78p7200l are dependent on board layout and will dictate the need for such added resistors. note 8. adding a series ferrite bead on vcc pins may be required for some pc board layout. external components (common to e3/ds3/sts-1) component tolerance value unit receiver termination resistor rtr 1% 75 ? receiver transformer turns ratio tr 3% 1:1 --- transmitter termination resistor rtt 1% 301 ? transmitter transformer turns ratio tt 3% 1:2ct --- external components (dependant on speed, nominal value) component tolerance sts-1 ds3 e3 unit loop filter capacitor clf 10% 0.047 0.047 0.047 f bias resistor rfo 1% 4.53 5.23 6.81 k ? note 9: advanced data sheet pin assignment, functions and external component values are subject to change.
78p7200l e3/ds3/sts-1 transceiver 20 78p7200l replacement for existing 78p7200 designs component variation for existing 78p7200 designs component 78p7200 78p7200l r1,r2 75 ? short (0 ? ) c2 82p not installed l2 6.8u not installed l1 0.47u not installed c1 1000p not installed c3 0.01 not installed t1 1:2 1:1 rtr 422 ? 75 ? input filter cpd 0.22u short (0 ? ) rlf2 100k ? not installed rlf1 6.04k ? not installed pll filter clf1 0.22u 0.047u ds3 301 ? 301 ? rtt e3 604 ? 301 ? ds3 5-15pf not installed transmitter ctt e3 3pf not installed power supply lvcc 4.7uh short (0 ? ) or ferrite bead
78p7200l e3/ds3/sts-1 transceiver 21 package pin designations (top view) 28-pin plcc (not drop-in compatible to 78p7200) 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 321282726 g n d l i n - g n d l i n + l p b k l o s v c c l b o e # r n a z t n e g t c l k v c c t x e n rfo gnd vcc gnd lo ut+ ic kp lo ut- rpo s rn eg rc lk gnd n/ c n/ c lf1 caution: use handling procedures necessary for a static sensitive component.
78p7200l e3/ds3/sts-1 transceiver 22 package pin designations (top view) 48-pin tqfp (not drop-in compatible to 78p7200) caution: use handling procedures necessary for a static sensitive component. rneg 1 gnd 3 rclk 2 rfo 4 gnd 5 gnd 6 vcc 7 gnd 8 e# 17 tpos 18 tneg 19 tclk 20 gnd 21 vcc 22 vcc 23 txen 24 47 gnd 48 gnd 46 gnd 45 gnd 44 lin- 43 gnd 42 lin+ 41 gnd 40 lpbk 38 vcc 37 vcc 36 gnd lf1 34 35 rpos 33 gnd 32 gnd 31 gnd 30 gnd 29 n/c lout- 13 gnd 14 lbo 15 gnd 16 gnd 9 10 lout+ 11 ickp 12 gnd 28 27 gnd 26 gnd 25 n/c 39 lo s vcc
78p7200l e3/ds3/sts-1 transceiver 23 mechanical drawing 28-pin plcc pin no. 1 ident. 0.495 (12.573) 0.485 (12.319) 0.495 (12.573) 0.485 (12.319) 0.456 (11.650) 0.450 (11.430) 0.456 (11.650) 0.450 (11.430) 0.075 (1.905) 0.065 (1.651) 0.045 (1.140) 0.020 (0.508) 0.050 (1.270) 0.016 (0.406) 0.020 (0.508) 0.390 (9.906) 0.430 (10.922) 0.165 (4.191) 0.180 (4.572)
78p7200l e3/ds3/sts-1 transceiver 24 mechanical drawing 48-pin tqfp ordering information part description order number package mark 28-pin plcc 78P7200L-IH 78P7200L-IH 48-pin tqfp 78p7200l-igt 78p7200l-igt advanced information: indicates a product is either in prototype testing or undergoing design evaluation prior to full production release. specifications are based on design goals or preliminary evaluation and are not guaranteed. small quantities are usually availab le and tdk semiconductor corporation should be consulted for current information. no responsibility is assumed by tdk semiconductor corporation for use of this product nor for any infringements of patents and trademarks or other rights of third parties resulting from its use. no license is granted under any patents, patent rights or trademarks o f tdk semiconductor corporation, and the company reserves the right to make changes in specifications at any time without notice. acc ordingly, the reader is cautioned to verify that the data sheet is current before placing orders. tdk semiconductor corp., 2642 michelle dr., tustin, ca 92780, (714) 508-8800, fax (714) 508-8877 www.tdksemic onductor.com ? 2001 tdk semiconductor corporation 03/06/01 - rev . c 0.2 (0.008) typ. index 1 8.7 (0.343) 9.3 (0.366) 1.40 (0.055) 1.60 (0.063) 8.7 (0.343) 9.3 (0.366) 0.50 (0.0197) typ. 6.8 (0.267) 7.2 (0.283) 0.0 (0) 0.20 (0.008) 0.60 (0.024) typ.

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